1. Field of the Invention
The present invention relates to an integrated circuit (IC) card, an IC card system, and an IC for the IC card, those operating with various supply voltages.
2. Description of the Prior Art
An IC card is a plastic card that incorporates an IC chip monolithically integrating a microcomputer circuit and a memory circuit. FIG. 1 shows an IC card system according to a prior art. The system includes an IC card 10 and a reader-writer 30 that receives and ejects the IC card 10. The reader-writer 30 is connected to a host computer (not shown), to mediate between the IC card 10 and the host computer.
The IC card 10 has terminals 11 to 15 to be connected to contact pins 31 to 35 of the reader-writer 30. The IC card 10 incorporates an IC chip monolithically integrating various circuits such as a central processing unit (CPU) 106 and a peripheral circuit 107 that includes an EEPROM 107a. The CPU 106 controls an interface with respect to the reader-writer 30 through the terminals 11 to 15 and an access operation on the EEPROM 107a.
The reader-writer 30 provides the IC card 10 with a supply voltage VDD, a clock signal CLK, and a reset signal RST. The reader-writer 30 has a control circuit 36 that controls the reception and ejection of the IC card 10 and data communication with the IC card 10 and host computer.
Recent LSIs employ smaller feature sizes and lower supply voltages. The operation voltage of LSI is migrating from 5 Volts to 3 Volts, or further 3 Volts to 2 Volts and below. Various manufacturers provide LSIs operating with different supply voltages. Accordingly, IC cards are required to operate on different supply voltages. Reader-writers of different manufacturers provide different supply voltages, and therefore, IC cards are required to stably operate on a wide range of supply voltages. FIG. 2 shows an example of an IC that operates on different supply voltages. This IC is disclosed in Japanese Unexamined Patent Publication No. 7-161929. The IC consists of a main IC 201, a voltage detector 202, a voltage switch 203, and an I/O buffer 204. The voltage switch 203 provides the main IC 201 with a predetermined low voltage even if an external supply voltage VDD fluctuates. The voltage switch 203 stepwise changes an operation voltage supplied to the I/O buffer 204 in response to a change in the supply voltage VDD detected by the voltage detector 202, thereby changing the amplitude of each I/O signal 205. This prior art controls only the voltage of each I/O signal in response to a change in the supply voltage VDD and is incapable of coping with phenomena ascribable to a change in the frequency of an input signal. If the frequency of any input signal fluctuates, the operation of the IC will be destabilized. If the main IC 201 receives a low supply voltage and if the frequency of a clock signal supplied to the main IC 201 exceeds the operating frequency of the main IC 201, the main IC 201 will be out of control. If a write instruction to write data into the EEPROM 107a is issued under this situation, data in the EEPROM will be destroyed.
To stabilize the operation of the IC card with respect to a wide range of supply voltages, the prior art must keep down the access conditions such as write conditions of the EEPROM 107a. For example, the prior art intentionally elongates a write time. This may increase power dissipation and lower the performance of the IC card system.
The prior art of FIG. 1 has no measures to cope with an abnormal supply voltage applied from the reader-writer 30 to the IC card 10. If the reader-writer 30 has a trouble such as quasi short-circuit in a part, the IC card 10, which operates on, for example, 5 V, may receive an abnormally low voltage of, for example, 3 V. In spite of the abnormally low supply voltage, the frequency of the clock signal CLK supplied to the IC card 10 is unchanged, i.e., high. On the other hand, the operating frequency of the CPU 106 of the IC card 10 usually drops as the supply voltage thereto drops, and therefore, the high-frequency clock signal destabilizes a write operation carried out by the CPU 106, or the CPU 106 may be out of control and destroy data in the EEPROM 107a.